The need for faster and more energy efficient processing of computer instructions has typically been at the forefront of development in processors and data processing systems. Traditional processors execute instructions in sequential order, i.e., subsequent instructions are executed only after the execution of the previous instruction is done. The effective execution speed of computer processors may be increased by speculative execution in which computer instructions are executed once the data necessary for that execution is available, even when previous instruction has not been executed. Speculation is particularly useful on handling branch instructions and memory instructions, which provides major performance advantages.
An example of speculative execution is branch prediction. In branch prediction, the processor predicts which path of a program branch to take and continues execution on the predicted path before the target of the branch instruction is computed. Other types of speculation include value prediction (predicting the value of a variable used by an arithmetic operation before it has been fetched or computed) and load-store dependence prediction (predicting that a variable value will not change from the execution of earlier instructions). Memory speculation is a performance enhancement feature that allows younger memory instructions to execute speculatively before all older memory instructions complete. For instance, the load instructions are often followed by instructions consuming data from them. By allowing load instructions to execute speculatively in advance, load data can be returned to its consumer instructions sooner, which offers a performance gain.
Correctness issues may occur when allowing a load instruction to execute speculatively before all older memory instructions complete. This would be an event when the speculation is in error (i.e., mis-speculation). For example, in a system that allows load instructions to execute speculatively before all older memory instructions have their address calculated, a load instruction may get executed while an older store instruction eventually targeting the same memory location is waiting for an address calculation. In such a case, the load instruction fails to see the latest update provided by the older store instruction. This further leads to stale data being returned and used by all its consumer instructions. Such speculatively executed instructions must be undone and the execution needs to be recovered. This process is done by returning the processor to a valid state before execution of the speculative instructions so that the correct instructions can be executed.
To maintain program correctness, current mis-speculation recovery mechanisms include a plurality of steps to be implemented to recover execution status back to a valid state. The steps include discarding all results and data inflight starting from the mis-speculated instruction in program order, redirecting control flow and restarting execution from the mis-speculated instruction detected in the previous step. After discarding all results from the mis-speculated instruction in program order, the execution status is reset to the last valid state. That is because all the results generated before the mis-speculated instruction must be valid and results and data inflight generated from and after the mis-speculated instruction must be all abandoned.
However, results and data that are completely independent of the mis-speculated load also get cleared and re-computed during discarding and regeneration of all results and data inflight starting from the mis-speculated load. This hugely affects the performance and the power efficiency of the processor for recovering from load mis-speculation. These inefficiencies further get widened up with the trend of increased depths of processor's internal buffers and issuing widths, which allows more instructions inflight and potentially more useful work (i.e., the independent data and its results) gets wasted.
Accordingly, techniques are desired for recovering from load mis-speculation execution that require less processing power such that only the affected instructions that either directly or indirectly consume data from the speculative load are re-executed instead of discarding and re-executing all instructions after the mis-speculated load.